A few months ago, AMD released information on their new technology for their Ryzen CPUs. AMD’s 3D V-Cache technology takes up to 64 megabytes of additional L3 cache & stacks it on top of Ryzen CPUs.
AMD 3D V-Cache Stack Chiplet Design Further Detailed, Ryzen 9 5950X With Boosted Game Cache
Data for modern AMD Zen 3 CPUs show that through their design to having the accessibility to allow for the 3D cache to be stacked from the beginning. This proves that AMD has worked on this technology for several years.
Now, Yuzo Fukuzaki from the website TechInsights provides more details about this new advancement in cache memory for AMD. Providing a closer look, Fukuzaki has found specific connection points on the Ryzen 9 5950X sample. There was also a note of additional space on the sample that creates accessibility for the 3D V-cache by providing more copper connection points.
The stacking installation process utilizes a technology called “through-silicon” vias, or TSV, which attaches the second layer of the SRAM to the chip through hybrid bonding. Using copper for the TSV instead of the usual solder allows for thermal efficiency and more bandwidth. This is in place of using solder to connect the two chips to each other.
He also notes in his LinkedIn article about the subject
To cope with #memory_wall problem, cache memory design is matter. Please take the chart in image attached, Cache density trend over process nodes. In the best timing by economical reasons, 3D memory integration on Logic can contribute to have higher performance. See #IBM #Power chips have huge amount of cache and strong trend. They can do it because of high end server CPU. With #Chiplet CPU integration started by AMD, they can use #KGD (Known Good Die) to get rid of low yield concern with monolithic large scale die. This innovation has been expected at 2022 in #IRDS (International Roadmap Devices and Systems) More Moore and AMD will do it.
TechInsights delved deeper into how the 3d V-Cache connects, so they worked their way through the technology in reverse, and have provided the following results with what was found, including TSV information and the space inside the CPU for the newer connections. This is the result:
- TSV pitch ; 17μm
- KOZ size ; 6.2 x 5.3 μm
- TSV counts rough estimation ; about 23 thousands!!
- TSV process position ; Between M10-M11 (15 Metals in total, starting from M0)
We can only speculate what AMD plans to use 3D V-Cache with its future structures, such as the Zen 4 architecture that is to be released in the near future. This new technology gives AMD processors an advantageous leap above Intel Technology, due to the L3 cache sizes becoming increasingly important as we see CPU core counts build in size every year.
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