A new AMD patent has been discovered which talks about the hybrid architecture consisting of Big and Little cores that are expected to be featured on next-gen Ryzen CPUs and APUs. There’ve been rumors that AMD is going to transition to a hybrid architecture with its next-gen chips, something that we will be getting with Intel later this year, and the ‘Task Transition’ patent more or less seems to confirm this.
AMD Gears Up For Its Hybrid Future, Patents ‘Task Transition’ Technology For Next-Gen Ryzen CPUs & APUs With Big/Little Cores
The Big and Little architecture which is a hybrid approach in which a CPU combines different core IPs for faster compute has been seen on ARM chips for a while now. More recently, Intel brought the technology to life on the x86 platform with its Lakefield SOC which combined Atom and Cove cores together. This hybrid approach is the next step forward for the x86 platform but we haven’t seen a wide-scale use of it so far, nor is current software ready to properly utilize the full potential of such architectures.
But with next-generation chips from Intel and AMD aiming to utilize a hybrid approach, it looks like a software update could soon be expected. AMD is indeed looking forward to bring this technology to its processors however, based on rumors, the plans are still in the early stage.
According to the latest patent (filed back in December of 2019), AMD talks about how tasks will be transitioned within heterogeneous processors. A Heterogenous approach could be interpreted in certain ways. The existing line of AMD APUs is heterogeneous since they pack two different IPs on the same die. But here, AMD is referring to the core architecture as being the heterogeneous implementation.
A method, system, and apparatus determine that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.
The patent lists down the two core IPs as ‘Big processors’ and ‘Little processors’. As we know, hybrid approaches always use faster cores for performance-oriented tasks and smaller cores for multi-threaded and efficiency-optimized tasks.
The patent shows that AMD is going to connect the two core IPs to the same interconnect while they will also be internally communicating with each other, sharing tasks such as core utilization, memory usage, memory access, idle/load power states, etc. The Big cores will be the ones doing the main decision-making.
AMD’s approach is definitely interesting and we know from rumors that they will be utilizing their next-gen Zen 5 architecture as the ‘Big Processor’ and Zen 4D architecture as the ‘Small Processor’ for Strix Point APUs. Those APUs aren’t expected till 2024 so it will be sometime before we see the hybrid architecture from AMD in action on next-gen Ryzen CPUs.
Meanwhile, as stated above, Intel’s Alder Lake chips will be bringing this approach later this year and huge updates are also expected to be coming to the new version of Windows such as new Scheduler optimizations to support the hybrid architecture. It all remains to be seen how well hybrid architectures are executed on the x86 mainstream consumer platforms in the next couple of years.
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