In addition to the two key EPYC & Instinct announcements, AMD also teased its next-gen Zen 4 powered Genoa and Bergamo CPU families. The Genoa and Bergamo EPYC chips will feature a brand new core architecture with the former offering up to 96 Zen 4 cores and the latter with an insane 128 Zen 4C core package.
AMD Next-Gen EPYC Genoa CPUs Feature Up To 96 Zen 4 Cores on 5nm, Bergamo Chips Feature Up To 128 Zen 4C Cores
AMD didn’t just unveil that they are bringing Genoa and Bergamo to the EPYC family but also unveiled a brand new chip architecture in the form of Zen 4C. The Zen 4C core was talked very recently in rumors as Zen 4D and we know a thing or two about it but first, let’s talk Genoa that utilizes the standard Zen 4 cores.
AMD EPYC Genoa CPUs – 5nm Zen 4 & Up To 96 Cores
Starting with the details, AMD has already announced that EPYC Genoa would be compatible with the new SP5 platform which brings a new socket so SP3 compatibility would exist up till EPYC Milan. The EPYC Genoa processors would also feature support for new memory and new capabilities. In the latest details, it is reported that the SP5 platform will also feature a brand new socket that will feature 6096 pins arranged in the LGA (Land Grid Array) format. This will be by far the biggest socket that AMD has ever designed with 2002 more pins than the existing LGA 4094 socket.
The socket will support AMD’s EPYC Genoa and future generations of EPYC chips. Talking about Genoa CPUs themselves, the chips will pack a mammoth 96 cores and 192 threads. These will be based on AMD’s brand new Zen 4 core architecture which is expected to deliver some insane IPC uplifts while utilizing the TSMC 5nm process node.
To get to 96 cores, AMD has to pack more cores in its EPYC Genoa CPU package. AMD is said to achieve this by incorporating a total of up to 12 CCD’s in its Genoa chip. Each CCD will feature 8 cores based on the Zen 4 architecture. That aligns with the increased socket size and we could be looking at a massive CPU interposer, even larger than the existing EPYC CPUs. The CPU is said to feature TDPs of 320W which will be configurable up to 400W.
Other than that, it is stated that AMD’s EPYC Genoa CPUs will feature 128 PCIe Gen 5.0 lanes, 160 for a 2P (dual-socket) configuration. The SP5 platform will also feature DDR5-5200 memory support which is some insane improvement over the existing DDR4-3200 MHz DIMMs. But that’s not all, it will also support up to 12 DDR5 memory channels and 2 DIMMs per channel which will allow up to 3 TB of system memory using 128 GB modules.
The main competitor of AMD’s EPYC Genoa lineup would be Intel’s Sapphire Rapids Xeon family which is expected to launch in 2022 too with PCIe Gen 5 and DDR5 memory support. The lineup was recently rumored to not get a volume ramp until 2023 which you can read more about over here. Overall, AMD’s Genoa lineup seems to be in great form after this leak and could be a major disruption for the server segment if AMD plays its cards right till Genoa’s launch by 2022.
AMD EPYC Bergamo CPUs – 5nm Zen 4C & Up To 128 Cores
There have been quite a few rumors going on about AMD’s EPYC Genoa being 128 core but it’s time to put that to rest. Based on what AMD has shown, the AMD EPYC Genoa lineup will feature TSMC’s 5nm process-based Zen 4 cores and a total of 96 of them. From what we can tell, AMD might have evaluated or tested Genoa with 128 cores internally but seemed to have featured 96 cores on the final design. The 96 core Genoa chips are what will compete against the non-HBM Sapphire Rapids Xeon CPUs.
But soon after Genoa, AMD is expected to launch another Zen 4 based server lineup known as Bergamo. The EPYC Bergamo chips will be featuring up to 128 cores and will be aiming the HBM powered Xeon chips along with server products from Apple and Google with higher core counts (ARM architecture). Both Genoa and Bergamo will utilize the same SP5 socket and the main difference is that Genoa is optimized for higher clocks while Bergamo is optimized around higher-throughput workloads.
In slides regarding Bergamo, it is clearly stated that the CPU lineup is optimized to offer breakthrough performance and power efficiency on the same socket and platform as Genoa. The main difference here is the reliance on the newer Zen 4c cores. The Zen 4 cores are said to be optimized for scale-out performance and offer significantly improved power efficiency along with density-optimized cache hierarchy.
It is rumored that AMD’s Zen 4c cores will be a stripped-down version of the standard Zen 4 cores with a redesigned cache and few features. The cores are also said to feature lower clock speeds to hit power consumption targets but the main goal is to increase the overall core density. While Zen 4 will rock 8 cores per chiplet, Zen 4D will rock up to 16 cores per chiplet. This will allow AMD to up lift its core count on next-generation processors and also scale up its multi-threaded performance.
It also makes sense why this chiplet design is heading to the EPYC Bergamo CPUs first as AMD is intended to further increase its leading multi-threaded performance in the server field. The reason to strip down the majority of features is that Zen 4D 16 core CCDs will take up the same space as standard 8 core Zen 4 CCDs. So a Zen 4D chiplet with all the Zen 4 features will lead to a bigger die size. It is also mentioned that Zen 4D might feature half the L3 cache of Zen 4, may remove AVX-512 support, and SMT-2 support isn’t confirmed. That looks a lot like the Gracemont cores on the Alder Lake CPUs which also feature lower clocks, per core L3 cache, and don’t support SMT.
It is likely that AMD is going to segmentize their Zen 4D and Zen 4 chips with Genoa being the full-fledged Zen 4 design while Bergamo being a hybrid design. Genoa will feature AVX-512 as the leaked documents from Gigabyte revealed while Bergamo will be aimed at applications that require core density over AVX-512 support. The number of memory channels might also increase to 12-channel DDR5 with Zen 4D powered Bergamo CPUs.
The AMD EPYC Genoa chip renders revealed a total of 12 Zen 4 CCD’s to reach 96 cores so a total of 16 Zen 4 CCD’s will be required for Bergamo to hit its 128 core count. The final die arrangement is definitely going to be an interesting sight and there are several rendered revisions from a series of leaks.
AMD EPYC CPU Families:
| Family Name | AMD EPYC Naples | AMD EPYC Rome | AMD EPYC Milan | AMD EPYC Milan-X | AMD EPYC Genoa | AMD EPYC Bergamo | AMD EPYC Turin |
|---|---|---|---|---|---|---|---|
| Family Branding | EPYC 7001 | EPYC 7002 | EPYC 7003 | EPYC 7003X? | EPYC 7004? | EPYC 7005? | EPYC 7006? |
| Family Launch | 2017 | 2019 | 2021 | 2022 | 2022 | 2023-2024? | 2024-2025? |
| CPU Architecture | Zen 1 | Zen 2 | Zen 3 | Zen 3 | Zen 4 | Zen 4 | Zen 5 |
| Process Node | 14nm GloFo | 7nm TSMC | 7nm TSMC | 7nm TSMC | 5nm TSMC | 5nm TSMC | 3nm TSMC? |
| Platform Name | SP3 | SP3 | SP3 | SP3 | SP5 | SP5 | SP5 |
| Socket | LGA 4094 | LGA 4094 | LGA 4094 | LGA 4094 | LGA 6096 | LGA 6096 | LGA 6096 |
| Max Core Count | 32 | 64 | 64 | 64 | 96 | 128 | 256 |
| Max Thread Count | 64 | 128 | 128 | 128 | 192 | 256 | 512 |
| Max L3 Cache | 64 MB | 256 MB | 256 MB | 768 MB? | 384 MB? | TBD | TBD |
| Chiplet Design | 4 CCD’s (2 CCX’s per CCD) | 8 CCD’s (2 CCX’s per CCD) + 1 IOD | 8 CCD’s (1 CCX per CCD) + 1 IOD | 8 CCD’s with 3D V-Cache (1 CCX per CCD) + 1 IOD | 12 CCD’s (1 CCX per CCD) + 1 IOD | 12 CCD’s (1 CCX per CCD) + 1 IOD | TBD |
| Memory Support | DDR4-2666 | DDR4-3200 | DDR4-3200 | DDR4-3200 | DDR5-5200 | DDR5-5600? | DDR5-6000? |
| Memory Channels | 8 Channel | 8 Channel | 8 Channel | 8 Channel | 12 Channel | 12 Channel | TBD |
| PCIe Gen Support | 64 Gen 3 | 128 Gen 4 | 128 Gen 4 | 128 Gen 4 | 128 Gen 5 | TBD | TBD |
| TDP Range | 200W | 280W | 280W | 280W | 320W (cTDP 400W) | 320W (cTDP 400W) | 480W (cTDP 600W) |
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