Organization of Memory Device

Organization of Memory Device

Modern memory has the same basic configuration as magnetic core memory although the rings have been replaced with electronic memory cells such as the D-Latch.

The cells are arranged so that each row represents a memory location where a binary value would be stored and the columns represent different bits of those memory locations. This is where the terminology “1K x 8” used in Section 12.1 comes from.

Memory is like a matrix where the number of rows identifies the number of memory locations in the memory and the number of columns identifies the number of bits in each memory location.

To store to or retrieve data from a memory device, the processor must place a binary number called an address on special inputs to the memory device. This address identifies which row of the memory matrix or array the processor is interested in communicating with, and enables it.

Once a valid address is placed on the address lines, the memory cells from that row are connected to bi-directional connections on the memory device that allow data either to be stored to or read from the latches. These connections are called the data lines. Three additional lines, chip select, read enable, and write enable, are used to control the transaction.

A decoder with n inputs has 2n outputs, exactly one of which will be active for each unique pattern of ones and zeros at its input. For example, an active-low 2-input decoder will have four outputs. A different output will equal zero for each unique input pattern while all of the other inputs will be ones.

An address decoder selects exactly one row of the memory array to be active leaving the others inactive. When the microprocessor places a binary number onto the address lines, the address decoder selects a single row in the memory array to be written to or read from.

For example, if 0112 = 310 is placed on the address lines, the fourth row of the memory will be connected to the data lines. The first row is row 0. The processor uses the inputs read enable and write enable to specify whether it is reading data from or writing data to the selected row of the memory array.

These signals are active low. When read enable is zero, we are reading data from memory, and when write enable is zero, we are writing data to memory. These two signals should never be zero at the same time.

Sometimes, the read enable and write enable signals are combined into a single line called R /W (pronounced “read write-bar”). In this case, a one on R /W initiates a data read while a zero initiates a write.

If latches are used for the memory cells, then the data lines are connected to the D inputs of the memory location latches when data is written, and they are connected to the Q outputs when data is read. The last input to the memory device shown in the image above is the chip select.

The chip select is an active low signal that enables and disables the memory device. If the chip select equals zero, the memory activates all of its input and output lines and uses them to transfer data.

If the chip select equals one, the memory becomes idle, effectively disconnecting itself from all of its input and output lines. The reason or this is that the typical memory device shares the address and data lines of a processor with other devices.

Rarely does a processor communicate with only one memory device on its data lines. Problems occur when more than one device tries to communicate with the processor over shared lines at the same time. It would be like ten people in a room trying to talk at once; no one would be able to understand what was being said.

The processor uses digital logic to control these devices so that only one is talking or listening at a time. Through individual control of each of the chip select lines to the memory devices, the processor can enable only the memory device it wishes to communicate with.

The processor places a zero on the chip select of the memory device it wants to communicate with and places ones on all of the other chip select inputs.